1. Field of the Invention
The present invention relates to a bus interface device.
2. Description of the Background Art
FIG. 11 is a block diagram showing a data processing system of an NIC (Network Interface Card) according to a background art. As the NIC, there is shown, for example, an ATMLAN board 1 (hereinafter referred to as a "board 1").
In the processing system, data transfer from a host memory 22 to a local memory 3 provided on the board 1 is performed through the following procedure.
Firstly, a host CPU 21 sends a source address SA, a destination address DA, and a data length DL of data to be transferred from the host memory 22, to a configuration register 15 provided on a bus interface LSI 1a in the board 1 through a buffer 2a provided on a host bus bridge 2. For convenience, these data transfers are shown by the arrows in the figure, but in practice, they are performed through a host bus 100.
From a host bus DMA controller 12 on the bus interface LSI 1a in the board 1, a request BQH to acquire the host bus 100 is transferred to a host bus arbiter 2b on the host bus bridge 2. The host bus arbiter 2b examines whether the host bus 100 may be acquired by the host bus DMA controller 12. If practicable, the host bus arbiter 2b sends a use permission GNTH of the host bus 100 to the host bus DMA controller 12. In practice, the request BQH and the use permission GNTH are also sent through the host bus 100.
The host bus DMA controller 12 which has acquired the host bus 100 sends the host memory 22 an output request RQ and the source address SA obtained from the configuration register 15 (actually through the host bus 100). Data stored in the source address SA is sent to a data transfer buffer 11a on the bus interface LSI 1a through the host bus 100.
When the data transfer buffer 11a is full, full signals FULL are sent to a local bus DMA controller 13 on the bus interface LSI 1a. The local bus DMA controller 13 sends a local bus arbiter 4 on the board 1 a request BQL to acquire a local bus 101. The local bus arbiter 4 examines whether the local bus 101 may be acquired by the local bus DMA controller 13. For example, it checks if the local bus 101 is already acquired by a protocol processor 5. If practicable, the local bus arbiter 4 sends a use permission GNIL of the local bus 101 to the local bus DMA controller 13. The local bus arbiter 4 may be provided on the bus interface LSI 1a.
The local bus DMA controller 13 which has acquired the local bus 101 sends the local memory 3 an input request WQ and the destination address DA obtained from the configuration register 15. Data stored in the data transfer buffer 11a are sequentially transferred to the local memory 3 through the local bus 101 and then held in the destination address DA.
Thus when data transfer from a host memory to a local memory is performed through a host bus and a local bus, the data transfer buffer 11a always causes delay in the background art. In addition, the host bus DMA controller 12 and the local bus DMA controller 13 operate independently, so that latency in bus acquisition occurs in both of the host bus and the local bus. This hinders improvement of data transfer rate.